UPDATE: Consideration for a PCMCIA (size) DSO Reference Design

Two "Software Defined Instruments" are presently in development. A 1-GHz bandwidth DSO with 1-Meg passive probes, and a 6-Ghz version with standard 50-Ohm inputs. (Inexpensive passive probes are possible, because of extremely small size and a long USB interface cable substituting for the probe leads.)

Paper in progress --- For this reference Design I will need to do everything myself. Finish the breadboard for the PC-Card DSO, the layout of a 4-layer PCMCIA circuit card, assemble and fully test several working samples and consult a law firm familiar with licensing procedures.

My main reason for a legal agreement is to prevent having the design being "killed" by a T&M Company. There is very strong evidenced that Tektronix has done that several times in the past. The "exclusiveness" of the license will be tied to a small "mark-up" percentage and a minimum annual sales of over $50 Million.

The problem is I never was a good "technician" and that's why it will take me a long time to get the prototype ready. I am an "architect" and my part of the work is finished. But if I have to dig the foundation of the house myself and lay every brick, every beam, and do all the plumbing, I can do it, because I know the materials and the processes. Will it be fast? Certainly not, because I might fall asleep while doing it, I hate this kind of work!

These "reference designs" will be on PCMCIA or Flash-card platform, but only with one interface provided. However, there will be enough board-space and suitable circuitry to incorporate several types of other interfaces, such as USB, PC-Card, Flash Card, Ethernet 10/100 and universal via FPGA. My general design objectives will be to realize all advantages of the new DIS digitizing concept, which are basically the ones named by Girish Mhatre as "insatiable demands" in the context of current system performance.

1.) Lowest cost, 2.) Smallest size, 3.) Lowest power consumption, 4.) High digitizing resolution (up to 12 bits) and finally, 5.) Architecture suitable for a 50 GHz Bandwidth.

The "reference designs" will have all customary features of high-end oscilloscopes, which, of course, will not be needed for most specialized applications, such as embedded waveform monitoring features for other systems. As I said in my paper on Software Defined Instruments: "A complete GHz DSO as a generic module might appear to be an over-kill, but since nearly all additional DSO-native features are in software, cost savings of not providing these would be minimal."

The design I am working on at this time is a low bandwidth 200MHz card with only 8 bit digitizing resolution. --- However, the system architecture is identical to the multi-Giga Hertz versions and the design will be my "test bed" to optimize the layout for signal integrity and minimal cross talk. The interface will be the simplified PCMCIA type for the Hand Spring PDA.

 For a detailed system description go to: Star Trek Tricorder

 

The same basic Motorola MC68C12B32 is also suitable for the 2 GHz and higher bandwidth designs, but as a version with several times the internal RAM and running at the standard 16 MHz clock frequency. Power consumption will be higher, but still within the PCMCIA limits. Here are the proposed layouts for other interface versions.

  

 

 

Universal Interface via low power FPGA

(200MHz -- 10 bit digitizing resolution)

 

 

 

 

 

Old style PCMCIA Interface (1994)

(2 GHz --- 12 bit digitizing resolution)

 

 

 

 

 USB interfaced circuit

 (Power from USB host)

 

 

 

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