Two Dimensional-Incremental-Sampling, the D²DSO

Modern Digital Oscilloscopes use "repetitive signal sampling" to obtain a higher sampling rate and bandwidth than would be possible by having their flash-converters work on single events only. If such a converter has the speed to take 10 samples of a single cycle sine-wave, the 'dots' in the wave shown in the upper left corner of Fig 1 would indicate the result. The large gapes between the sample points can be filled-in if the signal repeats, by taking additional samples during the next 50 or more repetitions. A timing circuit, in conjunction with the trigger pick-up can generate the addresses to interleave these 'in-between' samples in the proper order in memory.

FIG. 1 First three signal repetitions out of eight - for an 8 bit conversion.

While this conventional "repetitive sampling" method is basically a timing function, which is also called "equivalent time sampling", and its main purpose is to increase the effective sampling rate, it is not directly involved in the A to D conversion process. The novel method of "Two Dimensional-Incremental-Sampling (D²IS)" however, combines the two functions inseparably. Time and amplitude are both <incrementally> sampled and the repetitive nature of signals is used directly to facilitate A to D conversion, for which the data memory becomes an integral part of the conversion circuits.

For the sine wave signal shown in the upper left corner of Fig 1, the resulting memory content of the first D²IS operation is shown just below it. Before this first sampling sweep, the D2IS circuit had its memory filled with the number 128, which represents 1/2 the voltage level of its full range. This value became the reference input to a single latch-comparator chip, which compared the input signal against this reference. If the input signal was lower than the reference, 1/4 of full range (64) was subtracted from the value in memory, which made it 64; if the input signal was higher, the same amount (64) was added to the memory content and the new number is 192. These new memory values now become the reference voltages for the comparator during the next repetition of the input signal. At this second sampling sweep, 1/8 of full range (32) is added or subtracted to or from the previous memory contents. For the sampling of the third signal repetition, 1/16 of full range (16) is the change value for the memory contents. Now the sine-wave nature of the input signal can already be recognized, and after five more signal repetitions the digitizing result equals the flash-converter shown in the upper left picture, having accuracy better than 0.5%.

An engineer-reader will have recognized the "successive approximation" algorithm used to explain the D²IS concept. (One of many algorithms usable) Operations, however, are not the same as that of conventional circuits of this type which work with an unchanging input voltage, mostly provided by an analog "sample & hold" circuit, while the D²IS circuit works with changing inputs signals and uses a latching comparator chip as a sample & hold mechanism. This sample & hold feature of latching comparators is also a part of the flash-converters operations.

Depending on the signal frequency and speed of the hardware, the number of 'incremental' samples that can be taken per repetition can vary, just as it does for the 'complete' samples of a flash-conversion. The upper frequency limit for the method however, depends solely on the bandwidth performance of the latch-comparator. just as it depends on the bandwidth performance of the many latch-comparators inside the flash-converter chip for conventional methods.

Will D²IS need many more Signal-Repetitions than Conventional Methods?

The answer to this is surprising! While D²IS must use "Sequential Equivalent Time Sampling", as all ET-sampling scopes with bandwidth over 2 GigaHertz do (state of the art) there is a difference. Tektronix writes: "Sequential ET Digitizing utilizes one trigger for each sampling point in the record." It sounds as if it were a concept limitation, but this general industry definition for this mode is incorrect, it is only a limitation of known circuits. The above example of D²IS shows that it can be easily changed to a constant sampling rate. (It's part of the patent) The other ET-sampling technique, for scopes below 2 GigaHertz bandwidth, is "Random ET Sampling", for which Tektronix states "Random ET Digitizing allows for faster filling of the waveform record (usually)" -That too is incorrect. Sequential sampling at a constant rate will always be much faster than random sampling, which must follow a probability function. For the D²IS design with 1000 sampling points only 10% more signal repetitions are needed, and for the 2 GigaHertz design with 8000 sample points, about 50% less repetitions are needed. (The reader should not despair for lack of immediate understanding, Equivalent Time and "Random" sampling are concepts not easy to comprehend. One very knowledgeable test engineers, Stan Runyon, senior T&M editor of EETimes, made a New Years resolution (jokingly) to finally learn random sampling. Apparently, the "Old Masters" of Tektronix have not done so!)

What about Bandwidth?

It is interesting to note that the specifications for latch-comparator chips do not give the correct bandwidth when the comparator is used in a D²IS circuit. Total propagation delay of the comparator chip is inconsequential for the bandwidth of this circuit, and even the input to latch delay is only indirectly involved. What determines the bandwidth is the characteristic of the latch-delay versus input-overdrive, a part of the <dispersion> factor. E.g., the fast AD96685 comparator has a total propagation delay of 2.5ns and its latch delay is faster than that. What determines the D²IS circuit performance however, is only the latch-part of the listed 50ps-delay dispersion. The effect of this dispersion for sampled square-waves for instance is a rounding of the upper and lowers 20mV portions, the edges of the signal. This looks similar to what a misadjusted scope probe would do, but it cannot be corrected by just simply changing probe capacitance, it is frequency/phase related and will need a DSP algorithm to correct it. If you are somewhat familiar with mixer circuits in Radio designs, you know that only the “non-linear” parts of circuits will cause mixing and distortions. This “dispersion” factor of comparators has a “non-linear” part at the very low mile-Volts range and when the “least significant bit” of the digitizing process falls into that range some distortion of the wave-form happens. (I have the best intention to work on this, unfortunately I find myself somewhat "mathematically challenged".)

Disregarding a DSP/algorithm for the time being, what bandwidth performance can be achieved without it by commodity comparator chips on the market? Seven years ago the fastest comparator on the market provided about 2-GigaHertz bandwidth (PC Instruments, ISA board), but this year, the first "IndiumPhosphide" comparators are being sampled which, in my experience, will provide a bandwidth of 50 Gigahertz. (Compared to Silicon/Germanium, IndiumPhosphide has the advantage of lower power demands.)

What are the Advantages of D²IS?

While there is no difference in the functioning of the single latch-comparator in D²IS compared to the many latch-comparators in a flash-converter, performance constrains for the 255 comparator circuits inside a modern 8-bit flash-converter are much more stringent. E.g., any deviation in response time of one comparator compared to the others will show up as distortion for high frequency waveforms. That is one of the reasons why all 255 comparators are integrated on a single semiconductor chip. This helps to achieve the matching requirements, but it also makes it difficult to obtain the necessary high speed. A single or dual comparator can easily be build for very high speed with a power consumption of only 100 mW. To fabricate 255 of these high-speed devices on one chip, (While not quite multiplying the power consumption; 0.1 Watt X 255 would melt the chip.) will exceed practical limits. Therefor, the 255 comparators must be designed for slower speeds. One other (but minor) advantage of the "single" comparator for D²IS is the much higher input impedance compared to 255 in parallel. Another advantage is the greater input voltage range allowing for 12-bit conversion.

This reasoning becomes even more obvious for higher than 8 bit digitizing resolution. E.g., a 10-bit flash-converter needs 1023 comparator circuits, but for the D²IS converter only the DAC generating the reference for the single comparator chip must be a 10-bit device, for which speed is not critical. All that is required are two more signal repetitions to obtain a ten-bit resolution. These factors are the important criterion when evaluating the "Dual-Incremental-Sampling" (D²IS) technique. Bandwidth can be much higher, digitizing resolution much higher and power consumption orders of magnitude lower. And best of all, --- the cost can also be more than an order of magnitude lower!

What is the Trade-off for a DSO using D²IS?

The major trade-off is a return of some analog-scope characteristics. An analog-scope with non-storage CRT needs repetitive input signals to make even medium frequency waveforms visible. In essence, the analog scope does not work in 'real-time'; the additive storage capability of the phosphor screen is an essential part of the analog-scope's function. Repetitive inputs are also a necessity for all types of equivalent-time sampling DSOs, including D²IS, but all can display signals with very low repetition rate, which the analog scope cannot. The difference for the D²IS type is that it cannot use the "random sampling" mode. This brings back another analog-scope characteristic; namely the fact that signals cannot be captured much 'before' the trigger point. For the Time Domain Reflectometer, the TDR function, however, D²IS has no trade-off.

To provide for lower frequency real-time ranges, conventional DSOs are doing a time-base switchover to use their repetitive sampling circuits (the flash converters) also for the real-time mode. A DSO using a D²IS circuit must employ separate A/D converters. The first PalmScope/TDR design uses the internal A/D converter of its central micro-controller chip for the lower frequency ranges. (Audio, industrial) This is a compromise to reduce cost to a range below $500 and the power consumption to less than 500mW.

No other compromises are being made for this first design. The time-base has a dual Zoom feature, allowing expansion of the signal at a cursor point and also a novel instant anti-aliasing feature. Trigger controls include a histeresis and trigger hold-off adjustment. (A feature of high-end scopes) The 1/10 Probe-switch and the probe-type (current, high voltage, active probe, TDR, etc.) are automatically detected by the scope-controller for a change of vertical ranges and data display. The design is fully self-calibrating for time, amplitude and probe-type and has enough margins to compensate for "aging" and substandard components.

In short, the PalmScope is an Instrument designed for engineers by engineers, who 'love' engineering.

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